View AT5FC004_3273233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-megabyte flash memory pcmcia card AT5FC004 pin name function a0-a21 addresses d0-d15 data ce1 , ce2, we , oe , reg control signals cd , wp bvd1, bvd2 card status pin configuration features single power supply read and write voltage, 5 v 5% high performance 200 ns maximum access time 6 ms typical sector write cmos low power consumption 20 ma typical active current (byte mode) 400 m a typical standby current fully ms-dos compatible flash driver and formatter virtual-disk flash driver with 512 bytes/sector random read/write to any sector no erase operation required prior to any write zero data retention power batteries not required for data storage pcmcia/jeida 68-pin standard selectable byte- or word-wide configuration high re-programmable endurance built-in redundancy for sector replacement minimum 100,000 write cycles five levels of write protection prevent accidental data loss block diagram
description atmels flash memory card provides the highest system level performance for data and file storage solutions to the portable pc market segment. data files and applications programs can be stored on the AT5FC004. this allows oem manufacturers of portable system to eliminate the weight, power consumption and reliability issues associated with electro-mechanical disk-based systems. the AT5FC004 requires a single voltage power supply for total system operation. no batteries are needed for data re- tention due to its flash-based technology. since no high voltage (12 v) is required to perform any write operation, the AT5FC004 is suitable for the emerging "mobile" personal sys- tems. the AT5FC004 is compatible with the 68-pin pcmcia/jeida international standard. atmels flash memory cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. it can be read like any typical pcmcia sram or rom card. the card information structure (cis) can be written by the oem or by atmel at the attribute memory address space using a format utility. the cis appears at the beginning of the cards attribute memory space and defines the low-level organization of data on the pc card. the AT5FC004 contains a separate 2 kbyte eeprom memory for the cards attribute memory space. the third party software solutions such as award softwares cardware ? system and the scms flash file system (ffs), enables atmels flash memory card to emulate the function of essentially all the major brand personal computers that are dos/windows compatible. for some unique portable computers, such as the hp200/100/95lx series, the software driver and formatter are also available. the atmel driver and formatter utilizes a self- contained spare sector replacement algorithm, enabled by at- mels small 512-byte sectors, to achieve long term card reliability and endurance. block diagram 2 AT5FC004
storage temperature........................ -30c to +70c ambient temperature with power applied................................... -10c to +70c voltage with respect to ground, all pins (1) .......... -2.0 v to +7.0 v v cc (1) ............................................... -2.0 v to +7.0 v output short circuit current (2) .................... -200 ma *notice: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the card. this is a stress rating only and functional operation of the card at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe- riods may affect device reliability. notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during volt- age transients, inputs may overshoot v ss to -2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, outputs may overshoot to v cc +2.0 v for periods up to 20 ns. 2. no more than one output shorted at a time. duration of the short cir- cuit should not be greater than one second. conditions equal v out = 0.5 v or 5.0 v, v cc = max. absolute maximum ratings* pin capacitance (f = 1 mhz, t = 25c) (1) symbol parameter conditions typ max units c in1 address capacitance v in = 0 v 20 pf c out output capacitance v out = 0 v 20 pf c in2 control capacitance v in = 0 ( ce) 45 pf c i/o i/o capacitance v i/o = 0 v 20 pf note: 1. this parameter is characterized and is not 100% tested. d.c. and a.c. operating range AT5FC004-20 operating temperature (case) com. 0 o c - 70 o c v cc power supply 5 v 5% AT5FC004 3
pc card pin assignments i = input, o = output, i/o = bi-directional, nc = no connect pin signal i/o function 1 gnd ground 2 d3 i/o data bit 3 3 d4 i/o data bit 4 4 d5 i/o data bit 5 5 d6 i/o data bit 6 6 d7 i/o data bit 7 7 ce 1 i card enable 1 (1) 8 a10 i address bit 10 9 oe i output enable 10 a11 i address bit 11 11 a9 i address bit 9 12 a8 i address bit 8 13 a13 i address bit 13 14 a14 i address bit 14 15 we i write enable 16 nc no connect 17 v cc power supply 18 nc no connect 19 a16 i address bit 16 20 a15 i address bit 15 21 a12 i address bit 12 22 a7 i address bit 7 23 a6 i address bit 6 24 a5 i address bit 5 25 a4 i address bit 4 26 a3 i address bit 3 27 a2 i address bit 2 28 a1 i address bit 1 29 a0 i address bit 0 30 d0 i/o data bit 0 31 d1 i/o data bit 1 32 d2 i/o data bit 2 33 wp o write protect (1) 34 gnd ground pin signal i/o function 35 gnd ground 36 cd 1 o card detect 1 (1) 37 d11 i/o data bit 11 38 d12 i/o data bit 12 39 d13 i/o data bit 13 40 d14 i/o data bit 14 41 d15 i/o data bit 15 42 ce 2 i card enable 2 (1) 43 nc no connect 44 rfu reserved 45 rfu reserved 46 a17 i address bit 17 47 a18 i address bit 18 48 a19 i address bit 19 49 a20 i address bit 20 50 nc no connect 51 v cc power supply 52 nc no connect 53 nc no connect 54 nc no connect 55 nc no connect 56 nc no connect 57 nc no connect 58 nc no connect 59 nc no connect 60 nc no connect 61 reg i register select 62 bvd 2 o battery voltage detect 2 (2) 63 bvd 1 o battery voltage detect 1 (2) 64 d8 i/o data bit 8 65 d9 i/o data bit 9 66 d10 i/o data bit 10 67 cd 2 o card detect 2 (1) 68 gnd ground notes: 1. signal must not be connected between cards. 2. bvd = internally pulled up. 4 AT5FC004
pin description symbol name type function a0-a21 address inputs input address inputs are internally latched during write cycles. d0-d15 data input/output input/output data input/outputs are internally latched on write cycles. data outputs are latched during read cycles. data pins are active high. when the memory card is de-selected or the outputs are disabled the outputs float to tri-state. ce 1 , ce 2 card enable input card enable is active low. the memory card is de-selected and power consumption is reduced to standby levels when ce is high. ce activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers, segment decoders, and associated memory devices. oe output enable input output enable is active low and enables the data buffers through the card outputs during read cycles. we write enable input write enable is active low and controls the write function to the memory array. the target address is latched on the falling edge of the we pulse and the appropriate data is latched on the rising edge of the pulse. v cc pc card power supply pc card power supply for device operation (5.0 v 5%) gnd ground ground cd 1 , cd 2 card detect output when card detect 1 and 2 = ground the system detects the card. wp write protect output write protect is active high and indicates that all card write operations are disabled by the write protect switch. nc no connect corresponding pin is not connected internally. bvd 1 , bvd 2 battery voltage detect output internally pulled up. (there is no battery in the card.) reg register select input provide access to card information structure in the attribute memory device AT5FC004 5
memory card operations the AT5FC004 flash memory card is organized as an array of 8 individual at29c040a devices. they are logically defined as contiguous sectors of 512 bytes. each sector can be read and written randomly as designated by the host. there is no need to erase any sector prior to any write operation. also, there is no high voltage (12 v) required to perform any write operations. the common memory space data contents are altered in a simi- lar manner as writing to individual flash memory devices. on- card address and data buffers activate the appropriate flash de- vice in the memory array. each device internally latches address and data during write cycles. refer to the common memory operations table. byte-wide operations the AT5FC004 provides the flexibility to operate on data in byte-wide or word-wide operations. byte-wide data is available on d0-d7 for read and write operations ( ce 1 = low, ce 2 = high). even and odd bytes are stored in a pair of memory chip segments (i.e., s0 and s1) and are accessed when a0 is low and high respectively. word-wide operations the 16-bit words are accessed when both ce 1 and ce 2 are forced low, a0 = dont care. d0-d15 are used for word-wide operations read enable/output disable data outputs from the card are disabled when oe is at a logic- high level. under this condition, outputs are in the high-imped- ance state. the a20 and a21selects the paired memory chip seg- ments, while a0 decides the upper or lower bank. the ce 1 / ce 2 pins determine either byte or word mode operation. the output enable ( oe) is forced low to activate all outputs of the memory chip segments. the on-card i/o transceiver is set in the output mode. the AT5FC004 sends data to the host. refer to a.c. read waveforms drawing. standby operations when both ce 1 and ce 2 are at logic-high level, the AT5FC004 is in standby mode; i.e., all memory chip segments as well as the decoder/transceiver are completely de-selected at minimum power consumption. even in the byte-mode read operation, only one memory chip segment (even or odd) is active at any time. the other seven memory chip segments remain in standby. in the word-mode there are two memory chip segments in active and six in standby. write operations the AT5FC004 is written on a sector basis. each sector of 512 bytes can be selected randomly and written independently with- out any prior erase cycle. a9 to a19 specify the sector address, while a20 and a21 specifies the flash chip segment pair. within each sector, the individual byte address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. each byte pair to be programmed must have its high-to-low transition on we (or ce) within 150 m s of the low-to- high transition of we (or ce) of the preceding byte pair. if a high-to-low transition is not de- tected within 150 m s of the last low-to-high transition, the data load period will end and the internal programming period will start. all the bytes of a sector are simultaneously programmed during the internal programming period. a maximum write time of 10 ms per sector is self-controlled by the flash devices. refer to a.c. write waveforms drawings. write protection the AT5FC004 has five types of write protection. the pcmcia/jeida socket itself provides the first type of write protection. power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. a mechanical write protection switch provides a second type of write protection. when this switch is activated, we is internally forced high. the flash memory arrays are therefore write-dis- abled. the third type of write protection is achieved with the built-in low vcc sensing circuit within each flash device. if the exter- nal vcc is below 3.8 v (typical), the write function is inhibited. the fourth type of write protection is a noise filter circuit within each flash device. any pulse of less than 15 ns (typical) on the we, ce 1 or ce 2 inputs will not initiate a program cycle. the last type of write protection is based on the software data protection (sdp) scheme of the at29c040a devices. each of the sixteen devices needs to enable and disable the sdp indi- vidually. refer to the software data protected program- ming/disable algorithm tables for descriptions of enable and disable sdp operations. card detection each cd (output) pin should be read by the host system to de- termine if the memory card is properly seated in the socket. cd 1 and cd 2 are internally tied to the ground. if both bits are not detected, the system should indicate that the card must be re-inserted. cis data the card information structure (cis) describes the capabilities and specifications of a card. the cis of the AT5FC004 can be written either by the oem or by atmel at the attribute memory space beginning at address 00000h by using a format utility. the AT5FC004 contains a separate 2 kbyte eeprom memory for the cards attribute memory space. the attribute is active when the reg pin is driven low. d0-d7 are active during at- tribute memory access. d8-d15 should be ignored. odd order bytes present invalid data. refer to the attribute memory operations table. 6 AT5FC004
begin interleaving low 256 bytes and high 256 bytes select sector wait for a maximum of 10 ms load address/data of 512 bytes sector program complete memory card program routine byte mode begin low and high bytes simultaneously select sector wait for a maximum of 10 ms load address/data of 256 words sector program complete memory card program routine word mode common memory operations x = dont care, where dont care is either v il or v ih levels. pins reg ce 2 ce 1 oe we a0 d8-d15 d0-d7 read-only read (x8) (1) v ih v ih v il v il v ih v il high z data out-even read (x8) (2) v ih v ih v il v il v ih v ih high z data out-odd read (x8) (3) v ih v il v ih v il v ih x data out-odd high z read (x16) (4) v ih v il v il v il v ih x data out-odd data out-even output disable v ih xxv ih v ih x high z high z standby x v ih v ih x x x high z high z write-only write (x8) (1) v ih v ih v il v ih v il v il high z data in-even write (x8) (2) v ih v ih v il v ih v il v ih high z data in-odd write (x8) (3) v ih v il v ih v ih v il x data in-odd high z write (x16) (4) v ih v il v il v ih v il x data in-odd data in-even output disable v ih xxv ih v il x high z high z notes: 1. byte access - even. in this x8 mode, d0-d7 contain the "even" byte (low byte) of the x16 word. d8-d15 are inactive. 2. byte access - odd. in this x8 mode, d0-d7 contain the "odd" byte (high byte) of the x16 word. this is accomplished internal to the card by transposing d8-d15 to d0-d7. d8-d15 are inactive. 3. odd byte only access. in this x8 mode, d8-d15 contain the "odd" byte (high byte) of the x16 word. d0-d7 are inactive. a0 = x. 4. word access. in this mode d0-d7 contain the "even" byte while d8-d15 contain the "odd" byte. a0 = x AT5FC004 7
attribute memory operations x = dont care, where dont care is either v il or v ih levels. pins reg ce 2 ce 1 oe we a0 d8-d15 d0-d7 read-only read (x8) (1) v il vih v il v il v ih v il high z data out-even read (x8) v il vih v il v il v ih v ih high z not valid read (x8) v il vil v ih v il v ih x not valid high z read (x16) v il vil v il v il v ih x not valid data out-even output disable v il xxvihv ih x high z high z standby x v ih v ih x x x high z high z write-only write (x8) (1) v il v ih v il v ih v il v il high z data in-even write (x8) v il vih v il v ih v il v ih high z not valid write (x8) v il vil v ih v ih v il x not valid high z write (x16) v il vil v il v ih v il x not valid data in-even output disable v il xxv ih v il x high z high z note: 1. byte access - even. in this x8 mode, d0-d7 contain the "even" byte (low byte) of the x16 word. d8-d15 are inactive. 8 AT5FC004
d.c. characteristics, byte-wide operation symbol parameter condition min typ max units i li input leakagecurrent v cc = v cc max, v in = v cc or v ss 1.0 20 m a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 20 m a i sb v cc standby current v cc = v cc max, ce = v cc 0.2 v 0.5 1.0 ma i cc1 (1) v cc active read current v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 5 mhz 20 40 ma i cc2 v cc active write current ce = v il , we = v il , programming in progress 20 40 ma v il input low voltage 0.8 v v ih input high voltage 2.4 v v ol output low voltage i ol = 3.2 ma 0.40 v v oh output high voltage i oh = -2.0 ma 3.8 v notes: 1. one flash device active, 7 in standby. d.c. characteristics, word-wide operation symbol parameter condition min typ max units i li input leakagecurrent v cc = v cc max, v in = v cc or v ss 1.0 20 m a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 20 m a i sb v cc standby current v cc = v cc max, ce = v cc 0.2 v 0.5 1.0 ma i cc1 (1) v cc active read current v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 5 mhz 40 80 ma i cc2 v cc active write current ce = v il , we = v il , programming in progress 40 80 ma v il input low voltage 0.8 v v ih input high voltage 2.4 v v ol output low voltage i ol = 3.2 ma 0.40 v v oh output high voltage i oh = -2.0 ma 3.8 v notes: 1. two flash devices active, 6 in standby. AT5FC004 9
a.c. read characteristics symbol parameter min max units t rc read cycle time 200 ns t ce chip enable access time 200 ns t acc address access time 200 ns t oe output enable access time 100 ns t lz chip enable to output in low z 5 ns t df chip disable to output in high z 60 ns t olz output enable to output in low z 5 ns t df output disable to output in high z 60 ns t oh output hold time from first of address, ce, or oe change 5 ns t wc write recovery time before read 10 ms ac measurement level ac driving levels 0.0v 3.0v 1.5v input test waveforms and measurement level t r , t f < 5 ns output pin 5.0v 100pf 1.8k 1.3k output test load t oh t df t df t wc t oe t ce t lz t olz t acc t rc address addresses stable vcc oe we ce data power-up, standby output valid high z standby, power-down device and address selection output enabled data valid 5.0 v 0v a.c. read waveforms (1) note: 1. ce refers to ce 1 , and/or ce 2 10 AT5FC004
write cycle characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 10 ns t ah address hold time 60 ns t ds data set-up time 60 ns t dh data hold time 10 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 100 ns t ah t dh t wp t wph t ds t as t wc t blc byte address sector address oe we ce 1 ce 2 data a0 byte 0 byte 1 byte 510 byte 2 byte 511 a1-a8 a9-a19 a.c. write waveforms (byte mode) notes: 1. a20 and a21 specify the pair of at29c040a devices to be written, while a0 controls the selection of even and odd bytes. a0, a20, and a21 must be valid throughout the entire we low pulse. 2. a9 through a19 must specify the sector address during each high to low transition of we (or ce ). 3. oe must be high when we and ce are both low. 4. all bytes that are not loaded within the sector being pro- grammed will be indeterminate. AT5FC004 11
t ah t dh t wp t wph t ds t as t wc t blc byte address sector address oe we ce 1,2 data word 0 word 1 word 254 word 2 word 255 a1-a8 a9-a19 1. a20 and a21 specify the pair of at29c040a devices to be writ- ten; they must be valid throughout the entire we low pulse. a0 is dont care. 2. a9 through a19 must specify the sector address during each high to low transition of we (or ce ). 3. oe must be high when we and ce are both low. 4. all bytes that are not loaded within the sector being pro- grammed will be indeterminate. a.c. write waveforms (word mode) 12 AT5FC004
software data protected programming algorithm (1) device 0123 data address aa 00aaaa aa 00aaab aa 10aaaa aa 10aaab data address 55 005554 55 005555 55 105554 55 105555 data address a0 00aaaa a0 00aaab a0 10aaaa a0 10aaab writes enabled write bytes write bytes write bytes write bytes note: 1. load 3 bytes to corresponding flash chip segment individually to enable software data protection. AT5FC004 13
software data protected disable algorithm (1) device 0123 data address aa 00aaaa aa 00aaab aa 10aaaa aa 10aaab data address 55 005554 55 005555 55 105554 55 105555 data address 80 00aaaa 80 00aaab 80 10aaaa 80 10aaab data address aa 00aaaa aa 00aaab aa 10aaaa aa 10aaab data address 55 005554 55 005555 55 105554 55 105555 data address 20 00aaaa 20 00aaab 20 10aaaa 20 10aaab writes enabled write bytes write bytes write bytes write bytes note: 1. load 6 bytes to corresponding flash chip segment individually to disable software data protection. 14 AT5FC004
cardware ? may be trademarks of others. t acc (ns) ordering code package operation range 200 AT5FC004-20 pcmcia type 1 commercial (0 c to 70 c) ordering information 85.6 0.2 mm 10.0 min. (mm) 10.0 min. (mm) 54.0 0.1 mm 3.3 0.1 mm 35 34 front side back side 68 1 packaging information pcmcia, type 1 pc memory card dimensions in millimeters AT5FC004 15

▲Up To Search▲

Price & Availability of AT5FC004

	To Download AT5FC004 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .